A HIGH SPEED AND LOW POWER 8-BIT RAM-CAM BASED ON ARCHITECTURE DESIGN

M.Santhoshi ¹, S.Dhivya ²           

                                                                                                                 

 ¹PG student- Department of ECE -UCETW, Madurai, Tamilnadu-India                                                       

²Assistant professor, ECE Dept., UCETW, Madurai, Tamilnadu-India

            Content Addressable Memory (CAM) is a high performance search engine, which access the data based on its contents in a single clock cycle but the power and area overhead will increase. To overcome this drawback we need to reduce the power consumption of the CAM when we search the data. Most memory devices store and retrieve data by addressing specific memory location. As a result, this path often becomes the limiting factor for the systems that rely on fast memory access. Due to their parallel pattern matching property, CAMs are gaining increasing importance over Random Access Memory (RAM) in recent years, though design complexity and power consumption continue to remain the major drawbacks. The challenge in the design of a CAM cell is to reduce leakage power in its compare circuitry without sacrificing the speed. This paper describes a novel high-performance low power design of CAM block.