DELAY AND POWER ANALYSIS OF VHBCSE BASED RESPFFIR FILTER ON VARIOUS FPGA'S
R. Solomon Roach 1, N. Nirmal Singh 2, C. Sheeja Herobin Rani 3
1 Assistant Professor, Department of ECE, Cape Institute of Technology, Tamilnadu, India
2 Professor / Head, Department of ECE , V V College of Engineering, Tamilnadu, India.
3 Assistant Professor, Department of ECE, St. Xavier's Catholic College of Engineering , Tamilnadu, India.
In Reconfigurable Even Symmetric Parallel Fast Finite Impulse Response (RESPFFIR) filter's the coefficients are reconfigurable at real time. This reconfigurable property of the RESPFFIR filter is useful for the implementation of filters on FPGA. In the previous work the area, power and delay of the Vertical Horizontal Binary Common Sub expression Elimination (VHBCSE) technique based RESPFFIR was analyzed using Cadence RC tool. In this paper, the delay, power and device utilization of VHBCSE based RESPFFIR filter on various Field Programmable Gate Array (FPGA) were analyzed. The VHBCSE technique is used to reduce the number of Logical Operators (LO) and Logical Depth (LD) of the RESPFFIR filter on FPGA's. The 2-bit BCSE algorithm has been applied vertically and horizontally across neighboring coefficients to reduce the CSs that arise in the coefficients, which intern diminish LO and LD in constant multiplier. The delay, power and device utilization of VHBCSE based RESPFFIR on Spartan 6, Spartan 6 low power, Virtex5 and Virtex6 low power were analyzed using XILINX ISE tool. The analysis imply the Spartan 6 low power device consume low power and Virtex6 low power device have less delay when compared with other devices.
