R. Santhoshkumar
PG student- Department of ECE - Srividhya college of
Engineering and technology, Virudhunagar, Tamilnadu, India.
Content
addressable memory (CAM) offers high-speed search function in a single clock
cycle. Due to its parallel match-line (ML) comparison, CAM is power-hungry.
Thus, robust, high-speed and low-power ML sense amplifiers are highly
sought-after in CAM designs. In this paper, we introduce a parity bit that
leads to 39% sensing delay reduction at a cost of less than 1% area and power
overhead. Furthermore, we propose an effective gated-power technique to reduce
the peak and average power consumption and enhance the robustness of the design
against process variations. A feedback loop is employed to auto turn off the power
supply to the comparison elements and hence reduces the average power
consumption by 64%. The proposed design can work at a supply voltage down to
0.5 V.
